The present invention relates to a digital filtering arrangement and is particularly suited for use in a high speed pulse density modulation to pulse code modulation translation equipment.
British Pat. No. 1,436,878 discloses a pulse density modulation (PDM) to pulse code modulation (PCM) translation arrangement comprising a digital filter to which a PDM signal is applied and logic means to which the output of the filter is applied, the logic means being arranged to select every mth group of n pulses in the digital filter output. Typically the translation arrangement can be depicted schematically as shown in FIG. 1. A PDM signal, which is a continuous stream of binary pulses or bits is applied to a digital filter 10 which is constructed to suppress, as far as possible, high frequency noise. The filtered signals are then applied to a sampling circuit 11 which effectively selects every mth group of n pulses. For example, consider a system in which the PDM rate is 8.064 Mb/s (megabits per second). After filtering this can be regarded as an arbitrary stream of 14-bit words with a word rate of 8.064 Mw/s (megawords per second). If now every 504th 14-bit word is selected, the output becomes a PCM signal of 16 Kw/s (kilowords per second).
Such an arrangement is suitable for a speech channel of 0-4 KHz (kilohertz) bandwidth. The basic rate clock would not be expected to exceed a nominal 8 MHz (megahertz). However, a channel of 56-112 KHz bandwidth as required for frequency division multiplex (FDM) analog-to-digital (A/D) conversion, or 0-50 KHz for a possible music A/D, would need a basic clock rate of about 56 MHz (i.e. this is the presently used 4 MHz for speech scaled up by a factor of 14) and there is a technology problem when working at this speed. In particular the power consumption of integrated circuits becomes unacceptable.
The basic principles of a digital filter coupled with selective logic can be explained with reference to FIG. 2. An N-bit shift register 20 has N tap outputs, each tap output having an individual weighting function X applied thereto. Thus the output of tap 1 is weighted by the function X.sub.1, that of tap 2 by X.sub.2 and so on. For example, if the weighting functions are generally increasing up to tap N/2 and then decreasing, the filter can have an impulse response as indicated by the curve 21 in FIG. 2. The outputs of all the taps are summed in network 22. Now, if the delay between each tap is T equal to 1/f.sub.c, where f.sub.c is the basic input clock frequency, and the total length of the filter is N taps, then the repetition period of the filter is f.sub.s =NXT. If the output of the filter is sampled at a frequency of f.sub.c /NT, then the filter will receive a new set of data during each period and each bit will be uniquely weighted by only one of the respective tap weights according to its position in the time sequence. However, if the sampling rate is required to be four times f.sub.s each bit will be successively weighted by four separate weights during its progress through the filter. This weighting would normally occur at the prevailing basic clock frequency.